1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device manufacturing method employing a simplified process for forming a cylindrical capacitor of DRAM.
2. Description of Related Art
In association with recent progress toward miniaturizing of DRAM (Dynamic Random Access Memory), particularly 64-megabit DRAM, the capacitance of a capacitor becomes more difficult to ensure. However, the next generation of DRAM is considered to require a further increase in the capacitance of a capacitor. A method of manufacturing conventional 64 Mb DRAM, particularly a method of forming cylindrical capacitors of DRAM, employs a thick film surface roughening method, wherein even a step for forming a cylindrical capacitor involves a large number of processes. Therefore, the step assumes a complicated process flow.
FIG. 38 is a top view showing the structure of a storage node of a conventional cylindrical capacitor. FIGS. 39A through 50B are cross-sectional views arranged in sequential order of some of steps for forming a storage node of the conventional cylindrical capacitor. Throughout FIGS. 38 to 50B, identical reference numerals designate identical elements, and repetition of their explanations is omitted.
In FIG. 38, reference numeral 383 designates a transfer gate formed on a silicon substrate (not shown); 382 designates a transfer gate frame such as a TG383; 395 designates a polysilicon bit line; BC denotes a bit line contact; and SC denotes an storage node contact. Each of FIGS. 39 to 50 comprises drawings A and B. Drawings A are cross-sectional views taken along line A1-A2 shown in FIG. 38 (hereinafter referred to as "horizontal cross-sectional views"), and drawings B are cross-sectional views taken along line B1-B2 shown in FIG. 38 (hereinafter referred to as "vertical cross-sectional views").
FIGS. 39A and 39B show an oxide film 380 which is formed (between the transfer gate and the polysilicon bit line) over a wafer having TGs 383 and 384 formed thereon. FIG. 40A shows an oxide film 390 which is formed (at a position between the polysilicon bit line and the storage node) over the oxide film 380. As shown in FIG. 40B, each of the polysilicon bit lines 395 and 397 is of two-tier structure comprising WSi and a polysilicon film. As shown in FIGS. 41A and 41B, an etch pattern which enables a storage node to be formed so as to make direct contact with the substrate (such a storage node will hereinafter be referred to simply as a "storage node direct contact") is formed on the oxide film 390 by use of a photoresist 400.
As shown in FIGS. 42A and 42B, the oxide films 380 and 390 are subjected to dry etching along the etch pattern. In this case, the storage node direct contact is required to assume a diameter 412 of about 0.1 .mu.m and a depth 414 of about 1 .mu.m. As a result of a CF-based gas being used for dry-etching the oxide films 380 and 390, implanted C ions are considered to form a transformed SiC layer by union with the silicon substrate. The thus-transformed layer is called a damaged layer 410 and causes an increase in the resistance of the storage node direct contact. For this reason, the damaged layer 410 is eliminated through a chemical dry etching process performed through use of a down-flow etcher. As mentioned above, the storage node direct contact is required to assume a diameter 412 of about 0.1 .mu.m and a depth 414 of about 1 .mu.m. Further, there is needed an additional process for removing the damaged layer 410 through chemical dry etching (CDE).
As shown in FIGS. 43A and 43B, a polysilicon film 420 is formed on the oxide film 390 after removal of the photoresist 400. Subsequently, as shown in FIGS. 44A and 44B, the polysilicon film 420 is etched back to thereby form a polysilicon plug 430. Further, as shown in FIGS. 45A and 45B, a polysilicon film (for use in forming a storage node) 440 is formed over the polysilicon plug 430 and the oxide film 390. As shown in FIGS. 46A and 46B, an etch pattern is formed on the polysilicon film (for use in forming a storage node) 440 through use of a photoresist film 450. Then, as shown in FIGS. 47A and 47B, the polysilicon film 440 is etched to the oxide film 390.
As shown in FIGS. 48A and 48B, a frame 472 which will serve as the internal surface of a cylindrical storage node is formed on the surface of the oxide film 440 through a framing process (hereinafter referred to as a "RELACS process" or "RELACS processing"). An etch pattern is formed on the frame 472 through use of a negative photoresist 470. FIGS. 49A and 49B show the wafer after etching. As shown in FIGS. 50A and 50B, a cylindrical storage node is formed.
As set forth, the conventional method for manufacturing 64 Mb DRAM requires minute holes, and an expensive, high precision stepper and half-tone mask, etc., are required for ensuring registration margin corresponding to such a minute hole. To ensure a registration margin, there is also required a process for reducing a hole diameter. As a result, the diameter of a contact becomes smaller, which in turn increases contact resistance. Further, there are required an additional process for removing a damaged layer and a process for smoothing a high step through use of BPTEOS (BP-tetraethoxysilane), thereby resulting in an increase in the number of manufacturing processes.